Magnetic tunnel junction self-alignment in magnetic domain wall shift register memory devices

ABSTRACT

A magnetic domain wall shift register memory device includes a nanowire and a magnetic reference layer island disposed on the nanowire, wherein an interface between the nanowire and the magnetic tunnel junction island is a magnetic tunnel junction aligned with a width of the nanowire.

BACKGROUND

The present invention relates to magnetic domain wall shift registermemory devices, and more specifically, to a magnetic domain wall shiftregister memory device utilizing a magnetic tunnel junction (MTJ) thatis self-aligned to the nanowire that comprises the magnetic domain wallshift register.

Fabrication of a magnetic domain wall shift register memory devicerequires aligning one or multiple MTJs to one or multiple magneticnanowires. In the fabrication process, accurate alignment between theMTJ and the magnetic nanowire is crucial to obtaining a properlyfunctioning device.

Existing racetrack memory device designs utilize an integrated MTJ,where the nanowire acts as the free magnetic layer, and the referencemagnetic layer is patterned in a separate lithography step from thenanowire. This makes alignment and processing difficult, and oftennecessitates an MTJ that is narrower than the nanowire. Rounding alsooccurs due to optical effects of having a small hole versus a line inthe lithography masks. As such, much process optimization, includingtrial-and-error, is necessary during fabrication to properly align theMTJ on the nanowire.

SUMMARY

Exemplary embodiments include a magnetic domain wall shift registermemory device, including a magnetic nanowire and a reference magneticlayer island with a fixed magnetic orientation disposed on the nanowirewith an electrically insulating layer in between, wherein an interfacebetween the nanowire and the reference layer island with an electricallyinsulating layer in between is a magnetic tunnel junction aligned with awidth of the nanowire.

Additional exemplary embodiments include a magnetic domain wall shiftregister memory device, including a substrate, a nanowire disposed onthe substrate, and being a first magnetic material and a referencemagnetic layer island with a fixed magnetic orientation disposed on thenanowire, and being a second magnetic material, wherein an interfacebetween the nanowire and the reference magnetic layer island with anelectrically insulating layer in between is a magnetic tunnel junctionaligned with a width of the nanowire.

Further exemplary embodiments include a magnetic domain wall shiftregister memory device, including a nanowire patterned on a substrate, areference magnetic layer island with a fixed magnetic orientation islandpatterned on a portion of the nanowire, wherein the reference magneticlayer island with a fixed magnetic orientation with an electricallyinsulating layer in between is self-aligned on the portion of thenanowire.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with theadvantages and the features, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The forgoing and other features, and advantages ofthe invention are apparent from the following detailed description takenin conjunction with the accompanying drawings in which:

FIG. 1 illustrates a top plan view of an exemplary magnetic domain shiftregister memory device design;

FIG. 2 illustrates a top plan view of an exemplary multiple magneticdomain shift register memory device design;

FIG. 3 illustrates a flow chart for a method of MTJ self-alignment inmagnetic domain wall shift register memory devices in accordance withexemplary embodiments;

FIG. 4 illustrates an exemplary starting structure onto which theexemplary self-aligning MTJs in magnetic domain wall shift registermemory devices can be formed;

FIG. 5 illustrates an intermediate structure in which a lithographicstrip is patterned on a magnetic layer;

FIG. 6 illustrates an intermediate structure in which a top magneticstrip is formed on a magnetic layer;

FIG. 7 illustrates an intermediate structure in which a secondlithographic strip is patterned on a magnetic layer overlapping the topmagnetic strip;

FIG. 8 illustrates a final structure having an exemplary self-alignedMTJ disposed on a nanowire;

FIG. 9 illustrates an intermediate structure in which multiplelithographic strips are patterned on a magnetic layer overlapping thetop magnetic strip;

FIG. 10 illustrates a final structure having multiple exemplaryself-aligned MTJs disposed on multiple nanowires.

DETAILED DESCRIPTION

In exemplary embodiments, the systems and methods described hereininclude a magnetic domain wall shift register memory device, and afabrication method thereof, utilizing a self-aligned MTJ, which reducesthe accuracy needed in alignment and results in a higher yield and morereproducible device. The exemplary self-alignment systems and methodseliminate alignment mismatch and/or overlap errors when aligning one ormultiple MTJs to one or multiple magnetic nanowires. In exemplaryembodiments, a single extended lithographic patterning structure can beimplemented to fabricate multiple independent magnetic tunnel junctionsself-aligned to multiple independent magnetic nanowires.

FIG. 1 illustrates a top plan view of an exemplary magnetic domain shiftregister memory device design 100. As described herein, an exemplarymagnetic domain shift register memory device is fabricated implementinga self-aligned MJT readout. The design 100 demonstrates that a nanowire110 can be fabricated by standard lithographic techniques, and beoverlayed substantially perpendicular with lithographic strip 120 todefine an overlap region 130. It can be appreciated that the overlayregion 130 is thus self-aligned with the nanowire 110. As such, withfurther lithographic techniques, an MTJ can be fabricated within theoverlay region 130 and thus also be self-aligned with the nanowire 110.In this way, the need to dispose a pre-existing MTJ structure onto thenanowire 110 is eliminated thereby eliminating the inaccuracies involvedwith aligning MTJs as in the prior art.

FIG. 2 illustrates a top plan view of an exemplary multiple magneticdomain shift register memory device design 200. As described herein, anexemplary magnetic domain shift register memory device is fabricatedimplementing a self-aligned MJT readout. The design 200 demonstratesthat multiple nanowires 210 can be fabricated by standard lithographictechniques, and be overlayed substantially perpendicular withlithographic strip 220 to define overlap regions 230. It can beappreciated that the overlay regions 230 are thus self-aligned with therespective nanowires 210. As such, with further lithographic techniques,multiple MTJs can be fabricated within the overlay regions 230 and thusalso be self-aligned with the nanowires 210. In this way, the need todispose individual pre-existing MTJ structures onto the nanowires 210 iseliminated thereby eliminating the inaccuracies involved with aligningMTJs as in the prior art.

The magnetic domain shift register memory device designs 100, 200demonstrate implementation of MTJ self-alignment in magnetic domain wallshift register memory devices. FIG. 3 illustrates a flow chart for amethod 300 of MTJ self-alignment in magnetic domain wall shift registermemory devices in accordance with exemplary embodiments. FIG. 4illustrates an exemplary starting structure 400 onto which the exemplaryself-aligning MTJs in magnetic domain wall shift register memory devicescan be formed. The structure includes a substrate 410, onto which afirst magnetic layer 420 is disposed. A second magnetic layer 430 isfurther disposed on the first magnetic layer 420.

Referring again to FIG. 3, at block 310 a lithographic strip ispatterned on the second magnetic layer 430. FIG. 5 illustrates anintermediate structure 500 in which the lithographic strip is patternedon the second magnetic layer 430 with a photoresist pattern 510. Anysuitable lithographic technique can be implemented to pattern thelithographic strip. At block 320, the top magnetic strip 610 (see FIG.6) is formed by etching the surrounding exposed portions of the secondmagnetic layer 430. The patterned photoresist acts as a mask forsubtractive etching of the second magnetic layer 430. This subtractiveetch stops on the interface between the two magnetic layers 420, 430.Any suitable etching techniques such as, but not limited to, wetchemical etching and RIE are implemented. FIG. 6 illustrates anintermediate structure 600 in which a top magnetic strip 610 is formedon the first magnetic layer 420. At block 330, a nanowire and MTJ islandare patterned over the substrate 410. FIG. 7 illustrates an intermediatestructure 700 in which the top magnetic strip and nanowire resist strip710 are patterned on the first magnetic layer 420. FIG. 9 illustrates anintermediate structure 900 in which a top magnetic strip and multiplenanowire lithographic strips are patterned on the first magnetic layer420. Any suitable lithographic technique can be implemented to patternthe top magnetic strip and the nanowire lithographic strips. At block340, the nanowire 810 and MTJ island 820 (see FIG. 8) are formed byetching the surrounding exposed portions of the first magnetic layer 420and the exposed portions of the top magnetic strip 610. The patternedphotoresist acts as a mask for subtractive etching of the first magneticlayer 420 and the exposed part of the top magnetic strip 610 patternedfrom the second magnetic layer 430. The etching process retains the MTJisland 820 from the second magnetic layer 430 atop the nanowire 810 fromthe first magnetic layer 420. Any suitable etching techniques such as,but not limited to, wet chemical etching and RIE are implemented. FIG. 8illustrates a final structure 800 having an exemplary self-aligned MTJ820 disposed on the nanowire 810, which can support a magnetic domainwall shift register. FIG. 10 illustrates a final structure 1000 havingmultiple exemplary self-aligned MTJs 820 disposed on multiple nanowires810, which can support multiple magnetic domain wall shift registers.The interface between the MTJ island 820 and the nanowire 810 forms anMTJ 830 that precisely covers the width of the MTJ island 820 and thenanowire 810.

It can be appreciated that other fabrication steps are contemplated tocomplete the devices (e.g., the devices 100, 200) described herein. Forexample, patterning of the MTJ introduces device-to-device isolation inthe counter-electrode, but maintains electrical continuity between alldevices in the base electrode. Often negligible in fully integratedwafers, the resistance of the base electrode after MTJ patterning isgermane to the short loop. The use of a continuous planar base electrodeincurs additional measurement error at final electrical testing if thebase electrode possesses a high sheet resistance. Subject to theconstraint of emulating the stack used in fully functional wafers, themagnetic stack of the short loop will therefore include thick or lowresistivity films beneath the tunnel barrier. A commonly used,straightforward approach to patterning the MTJs is through the use of aconducting hard mask. The conducting mask is later utilized as aself-aligned stud bridging the conductive MT wiring to the activemagnetic films in the device. Such a processing scheme is among thesimplest and fastest ways of creating and contacting the MTJs, making itan ideal approach for use in the short loop. Choices for the hard maskare numerous, with necessary characteristics being etchability and aresistance that is negligible when compared with MTJ resistance.Refractory materials commonly used in the semiconductor industry such asTa, TaN, and TiN are suitable as masks for MTJ patterning. The MTJshapes are defined in the hard mask by transfer from a first photomasklevel in a process such as the following: apply resist/expose anddevelop/reactive ion etching (RIE) through hard mask/strip resist. Thepattern is further transferred downward to penetrate to (or through) thetunnel barrier, leaving behind a low-resistance base layer which coversthe entire wafer.

Other processing steps can include encapsulating the devices in adielectric. The encapsulation protects the devices while at the sametime forming the environment in which the attachment of contacts can beimplemented. The choice of encapsulation is determined from threerequirements: a) it must not damage the devices 100; b) it must adherewell to the substrate; and c) it should closely emulate the interlayerdielectrics (ILDs) that would be used in a fully integrated waferprocesses. For example, damage to the MTJs can arise from chemicalinteractions and thermal stress. Standard semiconductor-industrydielectrics typically are deposited or cured at temperatures around 400C, whereas degradation in submicron MTJs can set in at temperaturesbelow 350 C. Thus, a major challenge to the integrator of the shiftregister devices is the development and utilization of suitable lowtemperature dielectrics. Adhesion of the dielectric to the substrate canbe particularly problematic given the characteristics of the magneticfilms being used. Noble-metal-containing antiferromagnets can beparticularly difficult to adhere to, and, if exposed by the etching usedfor MTJ patterning, can require specialized surface-cleaning orsurface-preparation techniques to promote adhesion to the encapsulatingdielectric. The dielectric thickness is chosen such that it will bethick enough to provide the environment for the wiring level above theMTJs.

Other semiconducting fabrication processes can include planarization. Tofacilitate industry standard damascene copper wiring, the wafersgenerally undergo a gentle dielectric CMP process at this stage. Thepurpose of the CMP is to remove topography from the surface that iscaused by the underlying MTJs. This step is also the first check of theadhesion of the dielectrics to the underlying metal films, as well asthe cohesion of the metal films to each other. If the encapsulatingdielectrics are suitably planarizing in their deposition, this CMPplanarization step can be eliminated for faster turnaround time andpotentially higher yield.

After completion of the steps for the device development (e.g., layerformation, patterning, and encapsulation), the wiring is instituted inthe simplest manner consistent with the available tooling. Relying onwell-established semiconductor-industry techniques, a photomask definedtrench is etched into the dielectric with RIE, to be filled with a linerand high-conductivity copper. The depth of the trench is sufficient toexpose a portion of the conducting hard-mask stud (thecounter-electrode), while not so deep as to create a short circuit tothe planar base electrode. Endpointing during the trench RIE canfacilitate the proper choice of trench depth even for relatively thinhard-mask films. After the trench etching and a suitable cleaning step,the wiring liner film is deposited, along with a thin copper seed layer.This deposition is followed by the electroplating of copper tocompletely fill the trench and provide enough overburden so that theensuing CMP step will planarize the metal coincident with the surface ofthe dielectric. This final CMP step can be aggressive enough to causeshear failure of the films on the wafers, and care must be taken toprevent such delamination. A post-polish cleaning of the wafers is thefinal preparation step before electrical testing.

As such, it can be appreciated that the self-alignment systems andmethods described herein eliminate alignment mismatch and/or overlaperrors when aligning one or multiple MTJs to one or multiple magneticnanowires. In addition, a single extended lithographic patteringstructure can be used to fabricate multiple independent MTJsself-aligned to multiple independent magnetic nanowires.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of onemore other features, integers, steps, operations, element components,and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated

The flow diagrams depicted herein are just one example. There may bemany variations to this diagram or the steps (or operations) describedtherein without departing from the spirit of the invention. Forinstance, the steps may be performed in a differing order or steps maybe added, deleted or modified. All of these variations are considered apart of the claimed invention.

While the preferred embodiment to the invention had been described, itwill be understood that those skilled in the art, both now and in thefuture, may make various improvements and enhancements which fall withinthe scope of the claims which follow. These claims should be construedto maintain the proper protection for the invention first described.

What is claimed is:
 1. A magnetic domain wall shift register memorydevice, comprising: a magnetic nanowire; and a magnetic reference layerisland disposed on the nanowire, wherein an interface between themagnetic nanowire and the magnetic reference layer island is a magnetictunnel junction (MTJ) aligned with a width of the nanowire.
 2. Thedevice as claimed in claim 1 wherein the nanowire is a first magneticmaterial.
 3. The device as claimed in claim 2 wherein the magneticreference layer island is a second magnetic material.
 4. The device asclaimed in claim 1 wherein the nanowire is disposed on a substrate. 5.The device as claimed in claim 4 wherein the substrate is a firstmaterial.
 6. The device as claimed 5 wherein the nanowire is a firstmagnetic material disposed over the substrate and the magnetic referencelayer island is a second magnetic material disposed over the firstmagnetic material.
 7. The device as claimed in claim 6 wherein the firstmaterial is different from the first magnetic material and the secondmagnetic material.
 8. The device as claimed in claim 7 wherein the firstmagnetic material is different from the second magnetic material.
 9. Thedevice as claimed in claim 6 wherein the magnetic reference layer islandis formed by etching a portion of the second magnetic material.
 10. Thedevice as claimed in claim 9 wherein the nanowire is formed by etching aportion of the first magnetic material.
 11. A magnetic domain wall shiftregister memory device, comprising: a substrate; a nanowire disposed onthe substrate, and being a first magnetic material; and a magneticreference layer island disposed on the nanowire, and being a secondmagnetic material, wherein an interface between the nanowire and themagnetic reference layer island is an MTJ aligned with a width of thenanowire.
 12. The device as claimed in claim 11 wherein the substrate isa material different from the first magnetic material and the secondmagnetic material.
 13. The device as claimed in claim 12 wherein thefirst magnetic material is different from the second magnetic material.14. The device as claimed in claim 13 wherein the magnetic referencelayer island is formed by etching a portion of the second magneticmaterial and retaining the first magnetic material
 15. The device asclaimed in claim 14 wherein the nanowire is formed by etching a portionof the first magnetic material and a portion of the second magneticmaterial.
 16. A magnetic domain wall shift register memory device,comprising: a nanowire patterned on a substrate; a magnetic tunneljunction (MTJ) island patterned on a portion of the nanowire, whereinthe MTJ island is self-aligned on the portion of the nanowire.
 17. Thedevice as claimed in claim 16 wherein the substrate is a materialdifferent from the first magnetic material and the second magneticmaterial.
 18. The device as claimed in claim 17 wherein the firstmagnetic material is different from the second magnetic material. 19.The device as claimed in claim 18 wherein the MTJ island is formed byetching a lithographic strip disposed on the first magnetic material.20. The device as claimed in claim 19 wherein the nanowire is formed byetching a portion of the first magnetic material and the lithographicstrip.